FUTUR. Portal de la Producció Científica dels Investigadors de la UPC.

ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals

Total activitats: 11

Tipus: Grup de recerca
Tipus de grup: Grup de recerca UPC
Acrònim: ALBCOM
Adreça: Jordi Girona Salgado, 1-3. 08034 Barcelona, Spain
Localitat: Barcelona
URL: http://albcom.cs.upc.edu

Objectius: El grup de recerca ALBCOM uneix 19 reconeguts recercaires en Mètodes Formals; Disseny, Automatització i Verificació de VLSI; Algorismes i Complexitat; Bioinformàtica (veure http://albcom.cs.upc.edu/ per més detalls). La recerca que es realitza a ALBCOM té un important prestigi en la comunitat científica internacional, degut a la qualitat de la seva recerca, com mostren les seves publicacions, i a l'activitat en projectes de recerca i de transferència de tecnologia amb empreses i institucions del sector.
Paraules clau: Algorismes, Heuristiques, Metaheuristiques per a grafs i xarxes, Complexitat de problemes, Data science, Transformació de grafs

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Cases Muñoz, Rafel
(fins 2011-05-31)
Clariso Viladrosa, Robert
(fins 2003-01-31)
Clerici Martinez, Silvia Ines
(fins 2014-12-31)
Costa Gorgônio, Kyller
(fins 2006-09-30)
De San Pedro Martín, Javier
(fins 2016-09-30)
Frances Medina, Guillem
(fins 2009-06-14)

Frias Moya, Leonor
(fins 2010-06-13)
Galceran Oms, Marc
(fins 2010-06-30)
Garcia Chacon, Alina
(fins 2007-04-30)
Gascon Caro, Adrian
(fins 2013-07-31)
Gel Moreno, Bernat
(fins 2010-12-31)
Gimenez Llach, Omer
(fins 2010-10-31)

Hernandez Pibernat, Hugo
(fins 2012-05-06)
Julvez Bueno, Jorge Emilio
(fins 2008-09-28)
Maneva, Elitza Nikolaeva
(fins 2009-11-05)
Meng, Jiangtao
(fins 2005-10-15)
Muñoz Gama, Jorge
(fins 2015-02-28)
Ochremiak, Joanna Regina
(fins 2016-08-15)

Oliva Valls, Sergi
(fins 2012-08-31)
Perez Gimenez, Xavier
(fins 2003-08-31)
Roca Perez, Antoni
(fins 2016-11-30)
Sanchez Charles, David
(fins 2015-12-01)

Producció científica

1 a 11 de 11 resultats

Ordenar per:

Designing a branch target buffer for executing branches with zero time cost in a risc processor
Cortadella, J.; Jové, T.
EUROMICRO Conference
p. 573-580
Data de presentació: 1988-08-29
Presentació treball a congrés
The execution of branch instructions causes a loss of performance on pipelined processors. In the paper a new branch mechanism based on a branch target buffer is presented. It executes branches with zero time cost. In order to evaluate its performance improvement for several pipeline structures, an analytical model has been developed and simulations have been performed. The chip area required for its implementation is also considered. The performance increase and the simplicity of its design make it suitable to be included in a RISC-like processor
GSBL: an algebraic specification language based on inheritance
Clerici, S.I.; Orejas, F.
DOI: 10.1007/3-540-45910-3_5
Data de publicació: 1988-08-15
Capítol de llibre
Designing a branch target buffer for executing branches with zero time cost in a RISC processor
Cortadella, J.; Jové, T.
Microprocessing and microprogramming
Vol. 24, num. 1-5, p. 573-580
DOI: 10.1016/0165-6074(88)90113-5
Data de publicació: 1988-08
Article en revista
The execution of branch instructions causes a loss of performance on pipelined processors. In this paper a new branch mechanism based on a Branch Target Buffer is presented. It executes branches with zero time cost. In order to evaluate its performance improvement for several pipeline structures, an analytical model has been developed and simulations have been performed. The chip area required for its implementation is also considered. The performance increase and the simplicity of its design make it suitable to be included in a RISC-like processor.
A mechanism for reducing the cost of branches in RISC architectures
Gonzalez, A.; Llaberia, J.; Cortadella, J.
Microprocessing and microprogramming
Vol. 24, num. 1-5, p. 565-572
DOI: 10.1016/0165-6074(88)90112-3
Data de publicació: 1988-08
Article en revista
Execution of branch instructions is one of the main factors that prevents RISC processors from achieving their peak execution rate. A mechanism that attempts to execute branches with zero time cost is proposed. An analytical model that explains the behavior of the mechanism is presented. Simulation results show a significant performance improvement when compared with other schemes widely used in RISC architectures.
Evaluating A+B=K conditions in constant time
Cortadella, J.; Llaberia, J.
IEEE International Symposium on Circuits and Systems
p. 243-246
DOI: 10.1109/ISCAS.1988.14912
Data de presentació: 1988-06-07
Presentació treball a congrés
The authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, avoiding the carry propagation delay. This circuit can be used to detect a wide spectrum of conditions in branch instructions. It can improve the processor performance by advancing the evaluation of conditions and eliminating the pipeline delays produced by these operations.
Arbitration techniques for packet switching multistage interconnection networks
Domingo, J.; Llaberia, J.; Valero, M.; Cortadella, J.
International Conference on Supercomputing
p. 240-248
Data de presentació: 1988-05
Presentació treball a congrés
Presents some arbitration techniques to improve the performance of buffered multistage interconnection networks. In order to evaluate the performance they consider two parameters: throughput and mean service time. A study of the behavior of the network, focused in the average and the instantaneous length in the queues of the switching elements, shows that unbalanced load situations are frequent. One switching element has unbalanced load when one queue is almost full while the other is almost empty. The authors propose two decentralized arbitration mechanisms, respectively named lookahead arbitration and demand driven arbitration. Both arbitration methods try to modify the distribution of the packets in the network, so that unbalanced situations may be avoided or quickly eliminated when they occur. The evaluation is carried out through simulations. Results show that a network using these arbitration mechanisms can provide a better throughput than usual interconnection networks, and also show that the mean service time can be reduced.
A mechanism for reducing the cost of branches in RISC architectures
Gonzalez, A.; Llaberia, J.; Cortadella, J.
Symposium on Microprocessing and Microprogramming
p. 565-572
DOI: 10.1016/0165-6074(88)90112-3
Data de presentació: 1988
Presentació treball a congrés
Execution of branch instructions is one of the main factors that prevents RISC processors from achieving their peak execution rate. A mechanism that attempts to execute branches with zero time cost is proposed. An analytical model that explains the behavior of the mechanism is presented. Simulation results show a significant performance improvement when compared with other schemes widely used in RISC architectures.
Zero-delay cost branches in RISC architectures
Gonzalez, A.; Llaberia, J.; Cortadella, J.
IASTED International Symposium on Applied Informatics
p. 24-27
Data de presentació: 1988
Presentació treball a congrés
Execution of branch instructions is one of the main factors that reduce the performance of pipelines processors. A mechanism that attempts to execute branches with zero time cost is presented. The simulation results show that a 16-31% performance improvement is achieved when compared with other schemes widely used in RISC architectures.
Structural complexity I
Balcazar, J. L.; Diaz, J.; Gabarro, J.
DOI: 10.1007/978-3-642-79235-9
Data de publicació: 1988-01
Llibre
RISC: un nuevo enfoque en el diseño de procesadores
Cortadella, J.; Gonzalez, A.; Llaberia, J.
Mundo electrónico. Edición internacional
Vol. 1, num. 180, p. 49-57
Data de publicació: 1988-01
Article en revista
Incremental Construction and Analysis of Requirements Specifications (ICARUS)
Orejas, F.; Franch, X.; Clerici, S.I.
Projecte R+D+I competitiu
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