Coras, F.; Domingo, J.; Lewis, D.; Albert Cabellos-Aparicio IEEE-ACM transactions on networking Vol. 24, num. 1, p. 506-516 DOI: 10.1109/TNET.2014.2373398 Data de publicació: 2016-02 Article en revista
Concerns regarding the scalability of the interdomain routing have encouraged researchers to start elaborating a more robust Internet architecture. While consensus on the exact form of the solution is yet to be found, the need for a semantic decoupling of a node's location and identity is generally accepted as a promising way forward. However, this typically requires the use of caches that store temporal bindings between the two namespaces, to avoid hampering router packet forwarding speeds. In this article, we propose a methodology for an analytical analysis of cache performance that relies on the working-set theory. We first identify the conditions that network traffic must comply with for the theory to be applicable and then develop a model that predicts average cache miss rates relying on easily measurable traffic parameters. We validate the result by emulation, using real packet traces collected at the egress points of a campus and an academic network. To prove its versatility, we extend the model to consider cache polluting user traffic and observe that simple, low intensity attacks drastically reduce performance, whereby manufacturers should either overprovision router memory or implement more complex cache eviction policies.
Abadal, S.; Iannazzo, M.; Nemirovsky, M.; Albert Cabellos-Aparicio; Lee, H.; Alarcon, E. IEEE-ACM transactions on networking Vol. 23, num. 5 DOI: 10.1109/TNET.2014.2332271 Data de publicació: 2014-07-02 Article en revista
Networks-on-Chip (NoCs) are emerging as the way
to interconnect the processing cores and the memory within
a chip multiprocessor. As recent years have seen a significant
increase in the number of cores per chip, it is crucial to guarantee
the scalability of NoCs in order to avoid communication to
become the next performance bottleneck in multicore processors.
Among other alternatives, the concept of Wireless Network-on-
Chip (WNoC) has been proposed, wherein on-chip antennas
would provide native broadcast capabilities leading to enhanced
network performance. Since energy consumption and chip area
are the two primary constraints, this work is aimed to explore
the area and energy implications of scaling a WNoC in terms of
(a) the number of cores within the chip, and (b) the capacity of
each link in the network. To this end, an integral design space
exploration is performed, covering implementation aspects (area
and energy), communication aspects (link capacity) and networklevel
considerations (number of cores and network architecture).
The study is entirely based upon analytical models, which will
allow to benchmark the WNoC scalability against a baseline
NoC. Eventually, this investigation will provide qualitative and
quantitative guidelines for the design of future transceivers for
wireless on-chip communication.