This paper presents a CMOS RF second-order voltage-mode all-pass filter (APF) as a time delay cell. The proposed filter benefits from a simple structure; consisting of one transistor, three resistors, and one grounded capacitor and inductor. The filter reaches a group delay of 60 ps over a 10 GHz bandwidth, while achieving maximum delay-bandwidth-product (DBW) and it consumes only 10.3 mW power. On the other hand, an active inductor is used in the APF instead of a passive RLC tank in order to control the time delay and improve the size. In this case, the power consumption increases while time delay can be tuned. The proposed APF is designed and simulated in a TSMC 180 nm CMOS process.
In multiple receivers wireless power transfer (WPT) systems, it is preferable to retune the resonant frequency of every receiver to the transmitter operating frequency in front of frequency mismatches. This paper discusses a proposal for electronic tuning for WPT receivers by means of a variable active switch-mode inductance. The proposed method benefits from the gyrator concept to emulate a variable inductance. Instead of the conventional approach of linear amplifier based implementation of a gyrator, a switch-mode gyrator circuit is exploited for more efficient operation. Additionally, a PLL-like control is presented to enable self-tuning for the receiver resonant tank. Furthermore, a design-space characterization for the system dynamic behavior has been discussed to show the control robustness and the instabilities (including slow-scale and fast-scale chaotic instabilities) it may undergo.
Shirmohammadli, V.; Saberkari, A.; Martinez, H.; Alarcon, E. IEEE International Symposium on Circuits and Systems p. 1-4 DOI: 10.1109/ISCAS.2017.8050958 Data de presentació: 2017-05-30 Presentació treball a congrés
Shirmohammadli, V.; Saberkari, A.; Martinez, H.; Alarcon, E. IEEE International Conference on Electronics, Circuits and Systems p. 105-108 DOI: 10.1109/ICECS.2016.7841143 Data de presentació: 2016-12-13 Presentació treball a congrés
This paper deals with a comprehensive study and comparison on the conventional linear-assisted converter and a new structure named, LDO-assisted converter based on a new class-AB LDO regulator instead of the conventional linear one, in terms of efficiency, output ripple, and load transient response. The new structure reduces difference between input and output voltages and also switching frequency of the buck converter,
corresponding to higher power efficiency, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. A comparison analysis is done and the results are validated in HSPICE in a 0.18 µm CMOS process.
Shirmohammadli, V.; Saberkari, A.; Martinez, H.; Alarcon, E. Conference on Design of Circuits and Integrated Systems p. 1-4 DOI: 10.1109/DCIS.2016.7845356 Data de presentació: 2016-11-23 Presentació treball a congrés
In this paper, a new structure based on linear-assisted DC-DC buck converter principle is proposed. Using a segmented LDO regulator instead of the conventional linear one in the hybrid scheme, reduces the difference between input and output voltages and also the switching frequency of the buck converter, while the circuit provides a lower output ripple, better transient response. In addition, the proposal achieves higher power efficiency rather than the linear-assisted converter, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. A comparison analysis is done with regards to the mentioned performance indexes between the proposed structure and linear-assisted buck converter and the results are validated in HSPICE in a 0.35 µm CMOS process.