Nagashima, T.; Wei, X.; Bou, E.; Alarcon, E.; Kazimierczuk, Marian K., M.; Sekiya, H. IEEE transactions on industrial electronics Vol. 64, num. 4, p. 3227-3238 DOI: 10.1109/TIE.2016.2631439 Data de publicació: 2017-04-01 Article en revista
This paper presents a steady-state analysis of the isolated class-E2 converter outside nominal operation. By transforming the isolated class-E2 converter into the typical topology of the class-E inverter, the switching patterns can be comprehended on the parameter spaces easily. The output power and the power-conversion efficiency can be expressed as functions of circuit parameters such as coupling coefficient of the transformer, load resistance, and operating frequency. The class-E2 wireless power transfer (WPT) system was designed and implemented in this paper for verifying the analytical expressions. The analytical predictions of system performance against coupling-coefficient and load-resistance variations agreed with PSpice simulation and experimental results quantitatively, which showed the validity of the analytical expressions. Comparisons between the class-E2 and classD-E WPT systems are shown along with their discussions. Additionally, two application examples of the analytical expressions are introduced in this paper, which shows the usefulness of the analytical equations.
Rodríguez, J.; Delgado, M.; Masuch, J.; Rodriguez, A.; Alarcon, E.; Rodríguez, Á. IEEE transactions on industrial electronics Vol. 59, num. 2, p. 1310-1322 DOI: 10.1109/TIE.2011.2159695 Data de publicació: 2012-02 Article en revista
This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35- μm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10-3 with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 μA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply.