This article presents a fully-integrated CMOS output-capacitorless low-dropout voltage regulator (LDO). A capacitor multiplier based on a current-mode amplifier is embedded into the error amplifier of the aforementioned LDO to simultaneously enhance the dynamic specifications to load variations, stability by pole splitting, and power saving. The proposed LDO topology is designed and post simulated using a 0.35 mu m CMOS process to deliver a load current between 0-100 mA. The dropout voltage of the LDO is set to 200 mV for 2-3.5 V input voltage. A final benchmark comparison considering all relevant performance metrics is presented.