Saberkari, A.; Shirmohammadli, V.; Martinez, H.; Alarcon, E. International journal of circuit theory and applications Vol. 44, num. 5, p. 1156-1172 DOI: 10.1002/cta.2155 Data de publicació: 2016-05 Article en revista
This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power supply of RF power amplifiers (RFPA) to obtain favorable tradeoffs in terms of efficiency, switching ripple, bandwidth, and tracking capability. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency, low output ripples, and tracking capability with low ripples, simultaneously. A comparison analysis is done with regards to the mentioned performance indexes with the standard and three-level buck converters; in addition, the results are validated in HSPICE in BSIM3V3 0.35-µm CMOS process.
Saberkari, A.; Qaraqanabadi, F.; Shirmohammadli, V.; Martinez, H.; Alarcon, E. International journal of circuit theory and applications Vol. 44, num. 2, p. 460-475 DOI: 10.1002/cta.2087 Data de publicació: 2016-02 Article en revista
This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.
Digital control in switching power converters has been proposed and researched in recent years. However, one of the problems which arise in these circuits is that of quantization-induced limit cycle oscillations, which are generally considered to be undesirable. In this work, we investigate the addition of new control terms in the feedback loop of the system, in order to actively prevent these limit cycles from occurring. Firstly, the addition of a sinusoidal signal is considered, and then a more complicated signal which focuses on interrupting how the system switches between duty cycle levels is presented. The methods are effective in removing the limit cycle oscillations which arise in the system. Copyright (c) 2013 John Wiley & Sons, Ltd.
El Aroudi, A.; Rodriguez, E.; Orabi, M.; Alarcon, E. International journal of circuit theory and applications Vol. 39, num. 2, p. 175-193 DOI: 10.1002/cta.627 Data de publicació: 2011-02 Article en revista
In this paper, the dynamical behavior of a full bridge DC–AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period-doubling and Neimark–Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete-time model able to predict both instability phenomena is derived. The model is obtained without making the quasi-static approximation and it can be used to obtain the useful operation region in the multi-dimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided.