Abadal, S.; Mestres, A.; Iannazzo, M.; Solé-Pareta, J.; Alarcon, E.; Albert Cabellos-Aparicio International Workshop on Network-on-Chip Architectures p. 50-56 DOI: 10.1145/2685342.2685345 Data de presentació: 2014-12 Presentació treball a congrés
Network-on-Chip (NoC) is currently the paradigm of choice for covering the on-chip communication needs of multicore processors. As we reach the manycore era, though, electrical interconnects present performance and power issues that are exacerbated in the presence of multicast communications due to the point-to-point nature of NoCs. This dramatically limits the available design space in terms of manycore architecture, sparking the need for new solutions. In this direction, the use of wireless interconnects has been recently proposed as a complement of a wired plane. In this paper, the concept of Graphene-enabled Wireless Network-on-Chip (GWNoC) is introduced, which extends the native broadcast capabilities of existing wireless NoCs by enabling the per-core integration of antennas that radiate in the terahertz band (0.1 - 10 THz). Preliminary results on the feasibility of GWNoC are presented, covering implementation, on-chip networking and multiprocessor architecture aspects.
Abadal, S.; Iannazzo, M.; Nemirovsky, M.; Albert Cabellos-Aparicio; Lee, H.; Alarcon, E. IEEE-ACM transactions on networking Vol. 23, num. 5 DOI: 10.1109/TNET.2014.2332271 Data de publicació: 2014-07-02 Article en revista
Networks-on-Chip (NoCs) are emerging as the way
to interconnect the processing cores and the memory within
a chip multiprocessor. As recent years have seen a significant
increase in the number of cores per chip, it is crucial to guarantee
the scalability of NoCs in order to avoid communication to
become the next performance bottleneck in multicore processors.
Among other alternatives, the concept of Wireless Network-on-
Chip (WNoC) has been proposed, wherein on-chip antennas
would provide native broadcast capabilities leading to enhanced
network performance. Since energy consumption and chip area
are the two primary constraints, this work is aimed to explore
the area and energy implications of scaling a WNoC in terms of
(a) the number of cores within the chip, and (b) the capacity of
each link in the network. To this end, an integral design space
exploration is performed, covering implementation aspects (area
and energy), communication aspects (link capacity) and networklevel
considerations (number of cores and network architecture).
The study is entirely based upon analytical models, which will
allow to benchmark the WNoC scalability against a baseline
NoC. Eventually, this investigation will provide qualitative and
quantitative guidelines for the design of future transceivers for
wireless on-chip communication.