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TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies

Author
Canal, R.; Rubio, A.; ASenov, A.; Brown, A.; Miranda, M.; Zuber, P.; Gonzalez, A.; Vera, F.J.
Type of activity
Journal article
Journal
Procedia computer science
Date of publication
2011-12-22
Volume
7
First page
148
Last page
149
DOI
https://doi.org/10.1016/j.procs.2011.09.010 Open in new window
Repository
http://hdl.handle.net/2117/16283 Open in new window
URL
http://dx.doi.org/10.1016/j.procs.2011.09.010 Open in new window
Abstract
The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13 nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits.
Citation
Canal, R. [et al.]. TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies. "Procedia Computer Science", 22 Desembre 2011, vol. 7, p. 148-149.
Group of research
ARCO - Microarchitecture and Compilers
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants