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Design of Frequency Divider with Voltage Controlled Oscillator for 60 GHz Low Power Phase-Locked Loops in 65 nm RF CMOS

Type of activity
Theses
Other related units
Department of Electronic Engineering
Defense's date
2012-03-09
URL
http://hdl.handle.net/2117/94588 Open in new window
Abstract
Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 G...
Group of research
HIPICS - High Performance Integrated Circuits and Systems
Citation
Brandano, D. "Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS". Tesi doctoral, UPC, Departament d'Enginyeria Electrònica, 2012.

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