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A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance

Author
Ganapathy, S.; Canal, R.; Alexandrescu, D.; Costenaro, E.; Gonzalez, A.; Rubio, A.
Type of activity
Presentation of work at congresses
Name of edition
XXX IEEE International Conference on Computer Design
Date of publication
2012
Presentation's date
2012-10-02
Book of congress proceedings
2012 IEEE 30th International Conference on Computer Design (ICCD)
First page
472
Last page
477
Publisher
IEEE Computer Society Publications
DOI
https://doi.org/10.1109/ICCD.2012.6378681 Open in new window
Repository
http://hdl.handle.net/2117/18176 Open in new window
URL
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6378681&isnumber=6378602 Open in new window
Abstract
In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic powe...
Citation
Ganapathy, S. [et al.]. A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "2012 IEEE 30th International Conference on Computer Design (ICCD)". Montreal: IEEE Computer Society Publications, 2012, p. 472-477.
Keywords
Device scaling issues, Enhanced soft error tolerance, Memory cells, On-chip memories, SRAM, Variation-tolerant 4T-DRAM cell, eDRAM technology, embedded DRAM
Group of research
ARCO - Microarchitecture and Compilers
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants