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Speculative dynamic vectorization for HW/SW co-designed processors

Author
Kumar, R.; Martinez, A.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
21st International Conference on Parallel Architectures and Compilation Techniques
Date of publication
2012
Presentation's date
2012-09-19
Book of congress proceedings
Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques
First page
459
Last page
460
DOI
https://doi.org/10.1145/2370816.2370895 Open in new window
Project funding
MICROARQUITECTURA I COMPILADORS (ARCO)
URL
http://delivery.acm.org/10.1145/2380000/2370895/p459-kumar.pdf?ip=147.83.95.29&acc=ACTIVE%20SERVICE&CFID=291675087&CFTOKEN=32230426&__acm__=1363010645_a3442b0fd05ace495907edc1acbe7e27 Open in new window
Abstract
Hardware/Software (HW/SW) co-designed processors have emerged as a promising solution to the power and complexity problems of modern microprocessors. These processors utilize dynamic optimizations to improve the performance. However, vectorization, one of the most potent optimizations, has not yet received the deserved attention. This paper presents a speculative dynamic vectorization algorithm to explore its potential.
Keywords
HW/SW Co-designed processor, Speculation, Vectorization
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Kumar, Rakesh  (author and speaker )
  • Martinez Vicente, Alejandro  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )