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Disabling cache portions during low voltage operations - continuation of 8,103,830

Type of property
Invention patent
Number of request
13/342,016
Date of request
2012-10-16
Patent number
US 8,291,168 B2
Country
United States of America
Country of exploitation
United States of America
Owner organization
Intel Corporation
Project funding
MICROARQUITECTURA I COMPILADORS (ARCO)
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Wilkerson, Chris  (principal)
  • Khellah, Muhammad  (principal)
  • De, Vivek  (principal)
  • Zhang, Ming  (principal)
  • Abella Ferrer, Jaume  (principal)
  • Carretero Casado, Javier Sebastian  (principal)
  • Chaparro, Pedro  (principal)
  • Gonzalez Colas, Antonio Maria  (principal)
  • Vera Rivera, Francisco Javier  (principal)