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The migration prefetcher: anticipating data promotion in dynamic NUCA caches

Author
Lira, J.; Jones, T.; Molina, C.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
7th International Conference on High Performance and Embedded Architectures and Compilers
Date of publication
2012
Presentation's date
2012-01-24
Book of congress proceedings
7th International Conference on High-Performance and Embedded Architectures and Compilers: HiPEAC 2012: January 23-25 2012, Paris, France
First page
1
Last page
20
DOI
https://doi.org/10.1145/2086696.2086724 Open in new window
Project funding
MICROARQUITECTURA I COMPILADORS (ARCO)
URL
http://dl.acm.org/citation.cfm?doid=2086696.2086724 Open in new window
Abstract
The exponential increase in multicore processor (CMP) cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with a single, uniform access latency. Non-Uniform Cache Architecture (NUCA) designs have been proposed to address this problem. A NUCA divides the whole cache memory into smaller banks and allows banks nearer a processor core to have lower access latencies than those further away, thus mitigating the effects of the cache's internal wires....
Keywords
Cache memory, Memory hierarchy, Migration, NUCA, Prefetching
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Lira Rueda, Javier  (author and speaker )
  • Jones, Timothy M.  (author and speaker )
  • Molina Clemente, Carlos Maria  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )