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Layout Regularity for Design and Manufacturability

Author
Pons, M.
Type of activity
Theses
Other related units
Department of Electronic Engineering
Defense's date
2012-10-02
Repository
http://hdl.handle.net/2117/94699 Open in new window
URL
http://hdl.handle.net/2117/94699 Open in new window
Abstract
In nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, but also decreasing manufacturing yield. On the other hand, circuit designers and electronic design automation (EDA) developers have to reduce design turnaround time and provide the tools to cope with increasing design complexity and reduce the time-to-market. In this scenario, ...
Group of research
HIPICS - High Performance Integrated Circuits and Systems
Citation
Pons Solé, M. "Layout regularity for design and manufacturability". Tesi doctoral, UPC, Departament d'Enginyeria Electrònica, 2012.

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