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Variability mitigation mechanisms in scaled 3T1D-DRAM memories to 22 nm and beyond

Autor
Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on device and materials reliability
Data de publicació
2012-09-06
Volum
13
Número
1
Pàgina inicial
103
Pàgina final
109
DOI
https://doi.org/10.1109/TDMR.2012.2217497 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6296696 Obrir en finestra nova
Resum
It has been stated that 3T1D-DRAM cell is a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by variability. In this paper, it is shown that the 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation when they are scaled to nodes smaller than 22 nm. Furthermore, we present some strategies to mitigate the cell variability. Moreover, while scaling down capacitorless DRAM cells is a challenging trend, we also show how ...
Paraules clau
DRAM, temperature, variability
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
VIRTUOS - Virtualisation and Operating Systems

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