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Physical-aware system-level design for tiled hierarchical chip multiprocessors

Autor
Cortadella, J.; San Pedro, J. de; Nikitin, N.; Petit, J.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
International Symposium on Physical Design 2013
Any de l'edició
2013
Data de presentació
2013
Llibre d'actes
ISPD '13: Proceedings of the 2013 ACM International Symposium on Physical Design: March 24-27, 2013, Stateline, Nevada
Pàgina inicial
3
Pàgina final
10
Editor
ACM Press. Association for Computing Machinery
DOI
https://doi.org/10.1145/2451916.2451920 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/20573 Obrir en finestra nova
Resum
Tiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-e fficient many-core computing systems. At the early stages of the design of a CMP, physical parameters are often ignored and postponed for later design stages. In this work, the importance of physical-aware system-level exploration is investigated, and a strategy for deriving chip floorplans is described. Additionally, wire planning of the on-chip interconnect is performed, as i...
Citació
Cortadella, J. [et al.]. Physical-aware system-level design for tiled hierarchical chip multiprocessors. A: International Symposium on Physical Design. "ISPD '13: Proceedings of the 2013 ACM International Symposium on Physical Design: March 24-27, 2013, Stateline, Nevada". Stateline, Nevada: ACM Press. Association for Computing Machinery, 2013, p. 3-10.
Paraules clau
Chip multiprocessor, Floorplanning, Network-on-chip, Wire planning
Grup de recerca
ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals

Participants

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