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Circuit design of a novel adaptable and reliable L1 data cache

Autor
Seyedi, A.; Yalcin, G.; Unsal, O.; Cristal, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
GLSVLSI 2013 - 23rd ACM international conference on Great lakes symposium on VLSI
Any de l'edició
2013
Data de presentació
2013-05
Llibre d'actes
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Pàgina inicial
333
Pàgina final
334
DOI
https://doi.org/10.1145/2483028.2483129 Obrir en finestra nova
Projecte finançador
Computación de altas prestaciones V: arquitecturas, compiladores, sistemas operativos, herramientas y aplicaciones
Repositori
http://hdl.handle.net/2117/23133 Obrir en finestra nova
Resum
This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest reliability. Depending on the supply voltage level, Adapcache defines three operating modes: In high supply voltages, Adapcache provides reliability through single-bit parity. In middle range of supply voltages, Adapcache writes data to two separate cache-lines simultaneously in order to use o...
Citació
Seyedi, A. [et al.]. Circuit design of a novel adaptable and reliable L1 data cache. A: ACM Great Lakes Symposium on VLSI. "Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI". Parias: 2013, p. 333-334.
Paraules clau
CMOS integrated circuits, Cache memory, Design, Electric power supplies to apparatus, Fault tolerance, Fault tolerant computer systems, Separation

Participants

  • Seyedi, Azam  (autor ponent)
  • Yalcin, Gulay  (autor ponent)
  • Unsal, Osman Sabri  (autor ponent)
  • Cristal Kestelman, Adrian  (autor ponent)

Arxius