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Circuit design of a novel adaptable and reliable L1 data cache

Author
Seyedi, A.; Yalcin, G.; Unsal, O.; Cristal, A.
Type of activity
Presentation of work at congresses
Name of edition
GLSVLSI 2013 - 23rd ACM international conference on Great lakes symposium on VLSI
Date of publication
2013
Presentation's date
2013-05
Book of congress proceedings
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
First page
333
Last page
334
DOI
https://doi.org/10.1145/2483028.2483129 Open in new window
Project funding
Computación de altas prestaciones V: arquitecturas, compiladores, sistemas operativos, herramientas y aplicaciones
Repository
http://hdl.handle.net/2117/23133 Open in new window
Abstract
This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest reliability. Depending on the supply voltage level, Adapcache defines three operating modes: In high supply voltages, Adapcache provides reliability through single-bit parity. In middle range of supply voltages, Adapcache writes data to two separate cache-lines simultaneously in order to use o...
Citation
Seyedi, A. [et al.]. Circuit design of a novel adaptable and reliable L1 data cache. A: ACM Great Lakes Symposium on VLSI. "Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI". Parias: 2013, p. 333-334.
Keywords
CMOS integrated circuits, Cache memory, Design, Electric power supplies to apparatus, Fault tolerance, Fault tolerant computer systems, Separation

Participants

  • Seyedi, Azam  (author and speaker )
  • Yalcin, Gulay  (author and speaker )
  • Unsal, Osman Sabri  (author and speaker )
  • Cristal Kestelman, Adrian  (author and speaker )

Attachments