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Effectiveness of hybrid recovery techniques on parametric failures

Author
Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
Type of activity
Presentation of work at congresses
Name of edition
14th International Symposium on Quality Electronic Design
Date of publication
2013
Presentation's date
2013-03
Book of congress proceedings
Proceedings of the Fourteenth International Symposium on Quality Electronic Design: ISQED 2013: March 4-6, 2013: Santa Clara, California, USA
First page
258
Last page
264
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ISQED.2013.6523620 Open in new window
Repository
http://hdl.handle.net/2117/20160 Open in new window
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6523620&tag=1 Open in new window
Abstract
Modern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches are the most susceptible to voltage-noise induced failures because of process variations and reduced noise-margins thereby arbitrating whole processor's V ddmin. In this paper, we evaluate the effectiveness of a new class of hybrid techniques in improving cache yield through f...
Citation
Ganapathy, S. [et al.]. Effectiveness of hybrid recovery techniques on parametric failures. A: International Symposium on Quality Electronic Design. "Proceedings of the Fourteenth International Symposium on Quality Electronic Design: ISQED 2013: March 4-6, 2013: Santa Clara, California, USA". Santa Clara, California: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 258-264.
Keywords
Cache storage, Failure analysis, Integrated circuit reliability
Group of research
ARCO - Microarchitecture and Compilers
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants