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Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

Autor
Lorente, V.; Valero, A.; Sahuquillo Borrás, Julio; Petit, S.; Canal, R.; López Rodríguez, Pedro; Duato Marín, José Francisco
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
Design, Automation & Test in Europe Conference & Exhibition
Any de l'edició
2013
Data de presentació
2013-03-20
Llibre d'actes
Design, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings
Pàgina inicial
83
Pàgina final
88
DOI
https://doi.org/10.7873/DATE.2013.031 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/20567 Obrir en finestra nova
URL
http://dx.doi.org/10.7873/DATE.2013.031 Obrir en finestra nova
Resum
Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin. Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages belo...
Citació
Lorente, V. [et al.]. Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. A: Design, Automation and Test in Europe. "Design, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings". Grenoble: 2013, p. 83-88.
Paraules clau
DRAM, Memory, SRAM
Grup de recerca
VIRTUOS - Virtualisation and Operating Systems

Participants

  • Lorente Garcés, Vicente  (autor ponent)
  • Valero Breso, Alejandro  (autor ponent)
  • Sahuquillo Borrás, Julio  (autor ponent)
  • Petit Martí, Salvador  (autor ponent)
  • Canal Corretger, Ramon  (autor ponent)
  • López Rodríguez, Pedro  (autor ponent)
  • Duato Marín, José Francisco  (autor ponent)