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Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

Author
Lorente, V.; Valero, A.; Sahuquillo Borrás, Julio; Petit, S.; Canal, R.; López Rodríguez, Pedro; Duato Marín, José Francisco
Type of activity
Presentation of work at congresses
Name of edition
Design, Automation & Test in Europe Conference & Exhibition
Date of publication
2013
Presentation's date
2013-03-20
Book of congress proceedings
Design, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings
First page
83
Last page
88
DOI
https://doi.org/10.7873/DATE.2013.031 Open in new window
Repository
http://hdl.handle.net/2117/20567 Open in new window
URL
http://dx.doi.org/10.7873/DATE.2013.031 Open in new window
Abstract
Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin. Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages belo...
Citation
Lorente, V. [et al.]. Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. A: Design, Automation and Test in Europe. "Design, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings". Grenoble: 2013, p. 83-88.
Keywords
DRAM, Memory, SRAM
Group of research
VIRTUOS - Virtualisation and Operating Systems

Participants

  • Lorente Garcés, Vicente  (author and speaker )
  • Valero Breso, Alejandro  (author and speaker )
  • Sahuquillo Borrás, Julio  (author and speaker )
  • Petit Martí, Salvador  (author and speaker )
  • Canal Corretger, Ramon  (author and speaker )
  • López Rodríguez, Pedro  (author and speaker )
  • Duato Marín, José Francisco  (author and speaker )