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APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation

Author
Maric, B.; Abella, J.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
50th Annual Design Automation Conference
Date of publication
2013
Book of congress proceedings
DAC 50: Design Automation Conference: Conference Proceedings: Austin Convention Center, JUNE 2 – 6, 2013
First page
1
Last page
8
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1145/2463209.2488837 Open in new window
Repository
http://hdl.handle.net/2117/23156 Open in new window
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6560677 Open in new window
Abstract
Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown to be the main energy and area consumer in those chips. This paper proposes simple, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain Adaptive Performance- Predictable Low-Energy (APPLE) L1 cache designs based on replacing energy-hungry SRAM cells by more energy-e...
Citation
Maric, B.; Abella, J.; Valero, M. APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation. A: Design Automation Conference. "DAC 50: Design Automation Conference: Conference Proceedings: Austin Convention Center, JUNE 2 – 6, 2013". Austin: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 1-8.
Keywords
Cache, Faults, Low energy, Predictable performance
Group of research
CAP - High Performace Computing Group

Participants

  • Maric, Bojan  (author and speaker )
  • Abella Ferrer, Jaume  (author and speaker )
  • Valero Cortes, Mateo  (author and speaker )