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APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation

Autor
Maric, B.; Abella, J.; Valero, M.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
50th Annual Design Automation Conference
Any de l'edició
2013
Llibre d'actes
DAC 50: Design Automation Conference: Conference Proceedings: Austin Convention Center, JUNE 2 – 6, 2013
Pàgina inicial
1
Pàgina final
8
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1145/2463209.2488837 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/23156 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6560677 Obrir en finestra nova
Resum
Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown to be the main energy and area consumer in those chips. This paper proposes simple, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain Adaptive Performance- Predictable Low-Energy (APPLE) L1 cache designs based on replacing energy-hungry SRAM cells by more energy-e...
Citació
Maric, B.; Abella, J.; Valero, M. APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation. A: Design Automation Conference. "DAC 50: Design Automation Conference: Conference Proceedings: Austin Convention Center, JUNE 2 – 6, 2013". Austin: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 1-8.
Paraules clau
Cache, Faults, Low energy, Predictable performance
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Maric, Bojan  (autor ponent)
  • Abella Ferrer, Jaume  (autor ponent)
  • Valero Cortes, Mateo  (autor ponent)