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Yield estimation model for lithography hotspot distortions

Autor
Gomez, S.; Moll, F.
Tipus d'activitat
Article en revista
Revista
Electronics Letters
Data de publicació
2013-08-15
Volum
49
Número
17
Pàgina inicial
1066
Pàgina final
1068
DOI
https://doi.org/10.1049/el.2013.0469 Obrir en finestra nova
Projecte finançador
Design And Test Principles For Terascale Integrated Systems
MOLTO: Multilingual Online Translation
Repositori
http://hdl.handle.net/2117/20390 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6583109 Obrir en finestra nova
Resum
A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layout configurations showing that unidimensional designs may improve manufacturing yield.
Citació
Gomez, S.; Moll, F. Yield estimation model for lithography hotspot distortions. "Electronics Letters", 15 Agost 2013, vol. 49, núm. 17, p. 1066-1068.
Paraules clau
Hot spot, Manufacturing yield, Yield estimation, Yield loss, Yield modeling
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

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