Loading...
Loading...

Go to the content (press return)

Analysis of the Task Superscalar architecture hardware design

Author
Yazdanpanah, F.; Jimenez, D.; Alvarez, C.; Etsion, Y.; Badia, R.M.
Type of activity
Presentation of work at congresses
Name of edition
International Conference on Computational Science 2013
Date of publication
2013
Presentation's date
2013-06
Book of congress proceedings
2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)
First page
339
Last page
348
Publisher
Springer
DOI
https://doi.org/10.1016/j.procs.2013.05.197 Open in new window
Repository
http://hdl.handle.net/2117/23229 Open in new window
URL
http://www.sciencedirect.com/science/article/pii/S1877050913003402 Open in new window
Abstract
In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing som...
Citation
Yazdanpanah, F. [et al.]. Analysis of the Task Superscalar architecture hardware design. A: International Conference on Computational Science. "2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)". Barcelona: Springer, 2013, p. 339-348.
Keywords
Hardware task scheduler, Task Superscalar, VHDL
Group of research
CAP - High Performace Computing Group

Participants

Attachments