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Analysis of the Task Superscalar architecture hardware design

Autor
Yazdanpanah, F.; Jimenez, D.; Alvarez, C.; Etsion, Y.; Badia, R.M.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
International Conference on Computational Science 2013
Any de l'edició
2013
Data de presentació
2013-06
Llibre d'actes
2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)
Pàgina inicial
339
Pàgina final
348
Editor
Springer
DOI
https://doi.org/10.1016/j.procs.2013.05.197 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/23229 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S1877050913003402 Obrir en finestra nova
Resum
In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing som...
Citació
Yazdanpanah, F. [et al.]. Analysis of the Task Superscalar architecture hardware design. A: International Conference on Computational Science. "2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)". Barcelona: Springer, 2013, p. 339-348.
Paraules clau
Hardware task scheduler, Task Superscalar, VHDL
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

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