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Deconfigurable microprocessor architectures for silicon debug acceleration

Autor
Foutris, N.; Gizopoulos, D.; Vera, F.J.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
40th International Symposium on Computer Architecture
Any de l'edició
2013
Data de presentació
2013-06-23
Llibre d'actes
ISCA 2013: the 40th Annual International Symposium on Computer Architecture: conference proceedings: June 23-27, 2013: Tel-Aviv, Israel
Pàgina inicial
631
Pàgina final
642
DOI
https://doi.org/10.1145/2485922.2485976 Obrir en finestra nova
Resum
The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of “noise” in this phase is that large numbers of random test programs fail due to the same or similar...
Paraules clau
Deconfiguration, Microprocessor silicon debug, Validation
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants

  • Foutris, Nikos  (autor ponent)
  • Gizopoulos, Dimitris  (autor ponent)
  • Vera Rivera, Francisco Javier  (autor ponent)
  • Gonzalez Colas, Antonio Maria  (autor ponent)