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Deconfigurable microprocessor architectures for silicon debug acceleration

Author
Foutris, N.; Gizopoulos, D.; Vera, F.J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
40th International Symposium on Computer Architecture
Date of publication
2013
Presentation's date
2013-06-23
Book of congress proceedings
ISCA 2013: the 40th Annual International Symposium on Computer Architecture: conference proceedings: June 23-27, 2013: Tel-Aviv, Israel
First page
631
Last page
642
DOI
https://doi.org/10.1145/2485922.2485976 Open in new window
Abstract
The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of “noise” in this phase is that large numbers of random test programs fail due to the same or similar...
Keywords
Deconfiguration, Microprocessor silicon debug, Validation
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Foutris, Nikos  (author and speaker )
  • Gizopoulos, Dimitris  (author and speaker )
  • Vera Rivera, Francisco Javier  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )