Vés al contingut (premeu Retorn)

Deconfigurable microprocessor architectures for silicon debug acceleration

Foutris, N.; Gizopoulos, D.; Vera, F.J.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
40th International Symposium on Computer Architecture
Any de l'edició
Data de presentació
Llibre d'actes
ISCA 2013: the 40th Annual International Symposium on Computer Architecture: conference proceedings: June 23-27, 2013: Tel-Aviv, Israel
Pàgina inicial
Pàgina final
DOI Obrir en finestra nova
The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of “noise” in this phase is that large numbers of random test programs fail due to the same or similar...
Paraules clau
Deconfiguration, Microprocessor silicon debug, Validation
Grup de recerca
ARCO - Microarquitectura i Compiladors


  • Foutris, Nikos  (autor ponent)
  • Gizopoulos, Dimitris  (autor ponent)
  • Vera Rivera, Francisco Javier  (autor ponent)
  • Gonzalez Colas, Antonio Maria  (autor ponent)