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Physical planning for the architectural exploration of large-scale chip multiprocessors

Autor
San Pedro, J. de; Nikitin, N.; Cortadella, J.; Petit, J.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
2013 7th IEEE/ACM International Symposium on Networks on Chip
Any de l'edició
2013
Data de presentació
2013
Llibre d'actes
2013 Seventh IEEE/ACM International Symposium on Networks on Chip (NoCS)
Pàgina inicial
1
Pàgina final
2
DOI
https://doi.org/10.1109/NoCS.2013.6558399 Obrir en finestra nova
Projecte finançador
TIN2007-66523
Repositori
http://hdl.handle.net/2117/20300 Obrir en finestra nova
Resum
This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the m...
Citació
De San Pedro, J. [et al.]. Physical planning for the architectural exploration of large-scale chip multiprocessors. A: IEEE/ACM International Symposium on Networks-on-Chip. "2013 Seventh IEEE/ACM International Symposium on Networks on Chip (NoCS)". Tempe: 2013, p. 1-2.
Paraules clau
Microprocessor chips Computer networks Information systems
Grup de recerca
ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals

Participants