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Physical planning for the architectural exploration of large-scale chip multiprocessors

Author
San Pedro, J. de; Nikitin, N.; Cortadella, J.; Petit, J.
Type of activity
Presentation of work at congresses
Name of edition
2013 7th IEEE/ACM International Symposium on Networks on Chip
Date of publication
2013
Presentation's date
2013
Book of congress proceedings
2013 Seventh IEEE/ACM International Symposium on Networks on Chip (NoCS)
First page
1
Last page
2
DOI
https://doi.org/10.1109/NoCS.2013.6558399 Open in new window
Project funding
TIN2007-66523
Repository
http://hdl.handle.net/2117/20300 Open in new window
Abstract
This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the m...
Citation
De San Pedro, J. [et al.]. Physical planning for the architectural exploration of large-scale chip multiprocessors. A: IEEE/ACM International Symposium on Networks-on-Chip. "2013 Seventh IEEE/ACM International Symposium on Networks on Chip (NoCS)". Tempe: 2013, p. 1-2.
Keywords
Microprocessor chips Computer networks Information systems
Group of research
ALBCOM - Algorithms, Computational Biology, Complexity and Formal Methods

Participants