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BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

Autor
Arumi, D.; Rodriguez-Montanes, R.; Figueras, J.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
18th IEEE European Test Symposium
Any de l'edició
2013
Llibre d'actes
Proceedings of 18th IEEE European Test Symposium
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ETS.2013.6569389 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/20505 Obrir en finestra nova
URL
http://www.computer.org/csdl/proceedings/ets/2013/6376/00/06569389-abs.html Obrir en finestra nova
Resum
Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects built-in self test integrated circuit testing three-dimensional integrated circuits
Citació
Arumi, D.; Rodriguez, R.; Figueras, J. BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing. A: IEEE European Test Symposium. "Proceedings of 18th IEEE European Test Symposium". Avignon: Institute of Electrical and Electronics Engineers (IEEE), 2013.
Paraules clau
built-in self test integrated circuit testing three-dimensional integrated circuits
Grup de recerca
CRnE - Centre de Recerca en Ciència i Enginyeria Multiescala de Barcelona
QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat

Participants