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BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

Author
Arumi, D.; Rodriguez-Montanes, R.; Figueras, J.
Type of activity
Presentation of work at congresses
Name of edition
18th IEEE European Test Symposium
Date of publication
2013
Book of congress proceedings
Proceedings of 18th IEEE European Test Symposium
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ETS.2013.6569389 Open in new window
Repository
http://hdl.handle.net/2117/20505 Open in new window
URL
http://www.computer.org/csdl/proceedings/ets/2013/6376/00/06569389-abs.html Open in new window
Abstract
Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects built-in self test integrated circuit testing three-dimensional integrated circuits
Citation
Arumi, D.; Rodriguez, R.; Figueras, J. BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing. A: IEEE European Test Symposium. "Proceedings of 18th IEEE European Test Symposium". Avignon: Institute of Electrical and Electronics Engineers (IEEE), 2013.
Keywords
built-in self test integrated circuit testing three-dimensional integrated circuits
Group of research
CRnE - Barcelona Research Center in Multiscale Science and Engineering
QINE - Low Power Design, Test, Verification and Security ICs

Participants