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A self-adaptive hardware architecture with fault tolerance capabilities

Author
Soto, J.; Moreno, J.; Cabestany, J.
Type of activity
Journal article
Journal
Neurocomputing
Date of publication
2013-12-09
Volume
121
First page
25
Last page
31
DOI
https://doi.org/10.1016/j.neucom.2012.10.038 Open in new window
Repository
http://hdl.handle.net/2117/20434 Open in new window
URL
http://www.sciencedirect.com/science/article/pii/S0925231213004293 Open in new window
Abstract
This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of ce...
Citation
Soto, J.; Moreno, J.; Cabestany, J. A self-adaptive hardware architecture with fault tolerance capabilities. "Neurocomputing", 09 Desembre 2013, vol. 121, p. 25-31.
Keywords
Dynamic fault tolerance, MIMD, Self-adaptive, Self-placement, Self-replication, Self-routing
Group of research
CETpD - Technical Research Centre for Dependency Care and Autonomous Living
ISSET - Integrated Smart Sensors and Health Technologies

Participants