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Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells

Author
Amat, Esteve; Garcia, C.; Aymerich, N.; Rubio, A.; Canal, R.
Type of activity
Presentation of work at congresses
Name of edition
IEEE 56th International Midwest Symposium on Circuits and Systems
Date of publication
2013
Presentation's date
2013-08-05
Book of congress proceedings
Proceedings of the MWSCAS 2013 - 2013 IEEE 56th International Midwest Symposium on Circuits and Systems
First page
81
Last page
84
DOI
https://doi.org/10.1109/MWSCAS.2013.6674590 Open in new window
Project funding
Design And Test Principles For Terascale Integrated Systems
URL
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6674590 Open in new window
Abstract
3T1D-DRAM cells will still be operative with 7nm FinFETs but their performance is significantly degraded when factoring in variability. In order to improve the cell robustness against device process variation and high environment temperatures, we propose a Dual-VT strategy. Our results show a larger retention time, significant cell spread reduction and reliable behavior up to 100°C.
Group of research
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants

  • Amat Bertran, Esteve  (author and speaker )
  • Garcia Almudever, Carmen  (author and speaker )
  • Aymerich Capdevila, Nivard  (author and speaker )
  • Rubio Sola, Jose Antonio  (author and speaker )
  • Canal Corretger, Ramon  (author and speaker )