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A cache design for probabilistically analysable real-time systems

Autor
Kosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F. J.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
Design, Automation and Test in Europe 2013
Any de l'edició
2013
Data de presentació
2013-03
Llibre d'actes
Design, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013
Pàgina inicial
513
Pàgina final
518
Projecte finançador
Computación de Altas Prestaciones VI
Repositori
http://hdl.handle.net/2117/22448 Obrir en finestra nova
URL
http://dl.acm.org/citation.cfm?id=2485288.2485416 Obrir en finestra nova
Resum
Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. Probabilistic Timing Analysis (PTA) has emerged as a solution to reduce the amount of information needed to provide tight WCET estimates, although it imposes new requirements on hardware design. At cache level, so far only fully-associative random-replacement caches have been ...
Citació
Kosmidis, L. [et al.]. A cache design for probabilistically analysable real-time systems. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013". Grenoble: 2013, p. 513-518.
Paraules clau
Amount of information, Cache access, Hardware complexity, Hardware design, Random placement, Set-associative, Timing Analysis, Wcet analysis

Participants

  • Kosmidis, Leonidas  (autor ponent)
  • Abella Ferrer, Jaume  (autor ponent)
  • Quiñones Moreno, Eduardo  (autor ponent)
  • Cazorla Almeida, Francisco Javier  (autor ponent)