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Area-optimal transistor folding for 1-D gridded cell design

Autor
Cortadella, J.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computer-aided design of integrated circuits and systems
Data de publicació
2013-11
Volum
32
Número
11
Pàgina inicial
1708
Pàgina final
1721
DOI
https://doi.org/10.1109/TCAD.2013.2269680 Obrir en finestra nova
Projecte finançador
TIN2007-66523
Repositori
http://hdl.handle.net/2117/27265 Obrir en finestra nova
Resum
The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which consists of breaking large transistors into smaller ones (legs) that can be placed in the active area of the cell. In the 1-D style, diffusion sharing between differently sized transistors is not allowed, thus implying a significant area overhead when active areas with different si...
Citació
Cortadella, J. Area-optimal transistor folding for 1-D gridded cell design. "IEEE transactions on computer-aided design of integrated circuits and systems", Novembre 2013, vol. 32, núm. 11, p. 1708-1721.
Paraules clau
Cell generation, Design for manufacturability, Linear programming, Transistor folding, Transistor sizing
Grup de recerca
ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals

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