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Vectorizing for wider vector units in a HW/SW co-designed enviroment

Author
Kumar, R.; Martinez, A.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
HPCC 2013 - 15th International Conference on High Performance Computing and Communications
Date of publication
2013
Presentation's date
2013-11-13
Book of congress proceedings
The 15th IEEE international conference on high performance computing and communications and the 11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing: Zhangjiajie, Hunan Province, P.R. China, 13-15 November 2013
First page
518
Last page
525
DOI
https://doi.org/10.1109/HPCC.and.EUC.2013.80 Open in new window
URL
http://ieeexplore.ieee.org/document/6831962/ Open in new window
Abstract
Abstract—SIMD accelerators provide an energy efficient way of improving the computational power in modern microprocessors. Due to their hardware simplicity, these accelerators have evolved in terms of width from 64-bit vectors in Intel´s MMX to 512-bit wide vector units in Intel´s Xeon Phi. Although SIMD accelerators are simple in terms of hardware design, code generation for them has always been a challenge. This paper explores the scalability of SIMD accelerators from the code generation p...
Keywords
Dynamic optimization, HW/SW co-designed processor, Speculation, Vectorization
Group of research
ARCO - Microarchitecture and Compilers

Participants