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Vectorizing for wider vector units in a HW/SW co-designed enviroment

Autor
Kumar, R.; Martinez, A.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
HPCC 2013 - 15th International Conference on High Performance Computing and Communications
Any de l'edició
2013
Data de presentació
2013-11-13
Llibre d'actes
The 15th IEEE international conference on high performance computing and communications and the 11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing: Zhangjiajie, Hunan Province, P.R. China, 13-15 November 2013
Pàgina inicial
518
Pàgina final
525
DOI
https://doi.org/10.1109/HPCC.and.EUC.2013.80 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/6831962/ Obrir en finestra nova
Resum
Abstract—SIMD accelerators provide an energy efficient way of improving the computational power in modern microprocessors. Due to their hardware simplicity, these accelerators have evolved in terms of width from 64-bit vectors in Intel´s MMX to 512-bit wide vector units in Intel´s Xeon Phi. Although SIMD accelerators are simple in terms of hardware design, code generation for them has always been a challenge. This paper explores the scalability of SIMD accelerators from the code generation p...
Paraules clau
Dynamic optimization, HW/SW co-designed processor, Speculation, Vectorization
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants