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Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment

Autor
Kumar, R.; Martinez, A.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
25th International Symposium on Computer Architecture and HighPerformance Computing
Any de l'edició
2013
Data de presentació
2013-10-23
Llibre d'actes
2013 25th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2013: 23-26 October 2013, Porto de Galinhas, PE, Brazil: proceeding
Pàgina inicial
81
Pàgina final
88
Editor
IEEE Computer Society Publications
DOI
https://doi.org/10.1109/SBAC-PAD.2013.10 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/23295 Obrir en finestra nova
Resum
Leakage power is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this power. Therefore, reducing functional unit leakage has received much attention in the recent years. Power gating is one of the most widely used techniques to minimize leakage energy. Power gating turns off the functional units during the idle periods to reduce the leakage. Therefore, the amount of leakage energy savings is directly proportiona...
Citació
Kumar, R.; Martínez, A.; González, A. Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment. A: International Symposium on Computer Architecture and High Performance Computing. "2013 25th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2013: 23-26 October 2013, Porto de Galinhas, PE, Brazil: proceeding". Porto de Galinhas, Pernambuco: IEEE Computer Society Publications, 2013, p. 81-88.
Paraules clau
Devectorization, HW/SW co-designed processor, Leakage, Power gating
Grup de recerca
ARCO - Microarquitectura i Compiladors

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