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FPGA-based prototype of the task superscalar architecture

Author
Yazdanpanah, F.; Jimenez, D.; Alvarez, C.; Etsion, Y.; Badia, R.M.
Type of activity
Presentation of work at congresses
Name of edition
7th HiPEAC Workshop on Reconfigurable Computing
Date of publication
2014
Presentation's date
2013-01-21
First page
1
Last page
10
Abstract
In this paper, we present the first hardware implementation of a prototype of the Task Superscalar architecture; an experimental task-based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks out-of-order. The implemented hardware is based on a distributed design that can op erate in parallel and is easily scalable to manage hundreds of cores in the same way that Out-of-Order architectures manage functional units. Our p...
Keywords
FPGA, Task superscalar, VHD, hardware task scheduler
Group of research
CAP - High Performace Computing Group

Participants