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Hardware-efficient implementation of a femtocell/macrocell interference-mitigation technique for high-performance LTE-based systems

Author
Font, O.; Bartzoudis, N.; Payaró, M.; Pascual Iserte, A.
Type of activity
Presentation of work at congresses
Name of edition
23rd International Conference on Field Programmable Logic and Applications
Date of publication
2013
Presentation's date
2013-09
Book of congress proceedings
Proceedings FPL 2013
First page
1
Last page
4
DOI
https://doi.org/10.1109/FPL.2013.6645585 Open in new window
Repository
http://hdl.handle.net/2117/22070 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6645585 Open in new window
Abstract
This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS® testbed. The parallelization and concurrent resource utilization of the joint synchronization and interference detection processing blocks is covered with low-level details.
Citation
Font, O. [et al.]. Hardware-efficient implementation of a femtocell/macrocell interference-mitigation technique for high-performance LTE-based systems. A: International Conference on Field Programmable Logic and Applications. "Proceedings FPL 2013". Porto: 2013, p. 1-4.
Keywords
Field programmable gate arrays, Finite impulse response filters, Interference, OFDM, Real-time systems, Resource management, Synchronization
Group of research
SPCOM - Signal Processing and Communications Group

Participants

  • Font Bach, Oriol  (author and speaker )
  • Bartzoudis, Nikolaos  (author and speaker )
  • Payaró Llisterri, Miquel  (author and speaker )
  • Pascual Iserte, Antonio  (author and speaker )