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Hardware-efficient implementation of a femtocell/macrocell interference-mitigation technique for high-performance LTE-based systems

Autor
Font, O.; Bartzoudis, N.; Payaró, M.; Pascual Iserte, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
23rd International Conference on Field Programmable Logic and Applications
Any de l'edició
2013
Data de presentació
2013-09
Llibre d'actes
Proceedings FPL 2013
Pàgina inicial
1
Pàgina final
4
DOI
https://doi.org/10.1109/FPL.2013.6645585 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/22070 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6645585 Obrir en finestra nova
Resum
This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS® testbed. The parallelization and concurrent resource utilization of the joint synchronization and interference detection processing blocks is covered with low-level details.
Citació
Font, O. [et al.]. Hardware-efficient implementation of a femtocell/macrocell interference-mitigation technique for high-performance LTE-based systems. A: International Conference on Field Programmable Logic and Applications. "Proceedings FPL 2013". Porto: 2013, p. 1-4.
Paraules clau
Field programmable gate arrays, Finite impulse response filters, Interference, OFDM, Real-time systems, Resource management, Synchronization
Grup de recerca
SPCOM - Grup de Recerca de Processament del Senyal i Comunicacions

Participants

  • Font Bach, Oriol  (autor ponent)
  • Bartzoudis, Nikolaos  (autor ponent)
  • Payaró Llisterri, Miquel  (autor ponent)
  • Pascual Iserte, Antonio  (autor ponent)