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Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery

Autor
Upasani, G.; Vera, F.J.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
19th IEEE International On-Line Testing Symposium
Any de l'edició
2013
Data de presentació
2013-07-08
Llibre d'actes
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS): 8-10 July 2013: Chania, Crete, Greece
Pàgina inicial
85
Pàgina final
91
Editor
IEEE Computer Society Publications
DOI
https://doi.org/10.1109/IOLTS.2013.6604056 Obrir en finestra nova
Projecte finançador
MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
Repositori
http://hdl.handle.net/2117/21830 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/6604056/ Obrir en finestra nova
Resum
Cosmic radiation induced soft errors have emerged as a key challenge in computer system design. The exponential increase in the transistor count will drive the per chip fault rate sky high. New techniques for detecting errors in the logic and memories that allow meeting the desired failures in-time (FIT) budget in future chip multiprocessors (CMPs) are essential. Among the two major contributors towards soft error rate, silent data corruption (SDC) and detected unrecoverable error (DUE), DUE is ...
Citació
Upasani, G.; Vera, X.; Gonzalez, A. Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery. A: IEEE International On-Line Testing Symposium. "Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS): 8-10 July 2013: Chania, Crete, Greece". Chania: IEEE Computer Society Publications, 2013, p. 85-91.
Paraules clau
Accuracy, Acoustic waves, Detectors, Equations, Estimation, Mathematical model, Program processors
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants