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Terascale reliable adaptive memory systems

Total activity: 9
Type of activity
Competitive project
Funding entity
Commission of European Communities
Acronym
TRAMS
Funding entity code
FP7-248789-TRAMS
Amount
413.066,50 €
Start date
2010-01-01
End date
2012-12-31
Keywords
emerging research devices, future emerging technologies, late CMOS technology, process variability, reliability, reliability aware design, terascale memory systems, variability aware design
URL
http://cordis.europa.eu/project/rcn/93073_en.html Open in new window
http://cordis.europa.eu/projects/248789 Open in new window
Abstract
Technology projections indicate that future electronic devices will keep shrinking, being faster and consuming less energy per operation. In the next decade, a single chip will be able to perform trillions of operations per second and provide trillions of bytes per second in off-chip bandwidth. This is the so called Terascale Computing era, where terascale performance will be mainstream, available in personal computer, and being the building block of large data centers with petascale computing capabilities. However, these smaller devices will be much more susceptible to faults and its performance will exhibit a significant degree of variability. As a consequence, to unleash these impressive computing capabilities, a major hurdle in terms of reliability has to be overcome. The TRAMS project is the bridge for reliable, energy efficient and cost effective computing in the era of nanoscale challenges and teraflop opportunities.
The International Roadmap for Semiconductors (ITRS) report indicates that the Metal Oxide Semiconductor devices (MOS or MOS like devices) will be ultimately scaled down below 10 nm in several years. The CMOS technologies after the 16 nm technology generation are called Late CMOS technologies and will include novel multigate device architectures and novel channel and gate stack materials. Reliability issues are expected to be exacerbated to in sub-10 nm CMOS technology.
Beyond-CMOS emerging technologies will reach device dimensions reduction below 5 nm utilising among others, nanowire transistors, quantum devices, carbon nanotubes, graphene, or molecular electronics. Both the Late CMOS and the Beyond CMOS technologies hold the promise of a significant increase in device integration density complemented by an increase in system performance and functionality. However, a dramatic reduction in single device quality is also expected, complemented by increase in statistical variability, severe reduction of the signal to noise ratio, and severe reliability problems. Therefore,alternative device solutions and computation paradigms need to be investigated to keep the technology evolution pace in such a challenging scenario. Memory cells and, in general, system architectures intended for nanotechnologies (both late CMOS and emerging devices) need to address the variability and reliability problem and should be capable of solving or at least largely alleviating it. In order to build reliable nanosystems, the TRAMS project addresses a specific variability and reliability-aware analysis and design flow as well as a hierarchical tolerance design. In such a tera-device multicore system the main idea will be to define countermeasure techniques at circuit and architecture design levels. The objective of this project is to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort.
Scope
Europa
Plan
VII Programa Marc de la Unió Europea 2007-2013
Call year
2009
Funcding program
Cooperation Specific Programme
Funding subprogram
Information and Communication Technologies
Funding call
FET Open scheme
Grant institution
European Commission

Participants

Scientific and technological production

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