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Multi-level unified caches for probabilistically time analysable real-time systems

Author
Kosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F. J.
Type of activity
Presentation of work at congresses
Name of edition
34th Real-Time Systems Symposium
Date of publication
2013
Presentation's date
2013-12
Book of congress proceedings
2013 IEEE 34th Real-Time Systems Symposium (RTSS 2013): 3-6 December 2013: Vancouver, Canada
First page
360
Last page
371
Publisher
IEEEXPLORE
DOI
https://doi.org/10.1109/RTSS.2013.43 Open in new window
Project funding
Computación de Altas Prestaciones VI
Repository
http://hdl.handle.net/2117/22544 Open in new window
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6728890&tag=1 Open in new window
Abstract
Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, cache hierarchies severely challenge the computation of tight worst-case execution time (WCET) estimates. On the one hand, the analysis of the timing behaviour of a single level of cache is already challenging, particularly for data accesses. On the other hand, unifying data a...
Citation
Kosmidis, L. [et al.]. Multi-level unified caches for probabilistically time analysable real-time systems. A: IEEE Real-Time Systems Symposium. "2013 IEEE 34th Real-Time Systems Symposium (RTSS 2013): 3-6 December 2013: Vancouver, Canada". Vancouver: IEEEXPLORE, 2013, p. 360-371.
Keywords
Multi-level caches, Probabilistic timing analysis, WCET

Participants

  • Kosmidis, Leonidas  (author and speaker )
  • Abella Ferrer, Jaume  (author and speaker )
  • Quiñones Moreno, Eduardo  (author and speaker )
  • Cazorla Almeida, Francisco Javier  (author and speaker )