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Hardware-software coherence protocol for the coexistence of caches and local memories

Author
Alvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, N.; Ayguade, E.
Type of activity
Journal article
Journal
IEEE transactions on computers
Date of publication
2015-01-01
Volume
64
Number
1
First page
152
Last page
165
DOI
https://doi.org/10.1109/TC.2013.194 Open in new window
Project funding
Computación de altas prestaciones V: arquitecturas, compiladores, sistemas operativos, herramientas y aplicaciones
Repository
http://hdl.handle.net/2117/28300 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6616543 Open in new window
Abstract
Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and do not generate coherence traffic, but they suffer from poor programmability. When non-predictable memory access patterns are found, compilers d...
Citation
Álvarez, L. [et al.]. Hardware-software coherence protocol for the coexistence of caches and local memories. "IEEE transactions on computers", 01 Gener 2015, vol. 64, núm. 1, p. 152-165.
Keywords
Architecture, Coherence protocol, Efficient, Hybrid memory system, Lcal memories, Performance, Scratchpad memories, Systems
Group of research
CAP - High Performace Computing Group

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