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INFORMER: an integrated framework for early-stage memory robustness analysis

Author
Ganapathy, S.; Canal, R.; Alexandrescu, D.; Costenaro, E.; Gonzalez, A.; Rubio, A.
Type of activity
Presentation of work at congresses
Name of edition
17th Design, Automation and Test in Europe
Date of publication
2014
Presentation's date
2014-03-24
Book of congress proceedings
Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014
First page
1
Last page
4
Publisher
European Interactive Digital Advertising Alliance (EDAA)
DOI
10.7873/DATE2014.046
Project funding
Design And Test Principles For Terascale Integrated Systems
MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
Microarquitectura i compiladors (ARCO)
Repository
http://hdl.handle.net/2117/23206 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6800247 Open in new window
Abstract
With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware design paradigm requires a holistic perspective of memory-wide metrics such as yield, power and performance. However, accurate estimation of such metrics is largely dependent on circuit implementation styles, technology parameters and architecture-level specifics. In this p...
Citation
Ganapathy, S. [et al.]. INFORMER: an integrated framework for early-stage memory robustness analysis. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014, p. 1-4.
Keywords
SRAM chips, circuit simulation, failure analysis, integrated circuit reliability, radiation hardening (electronics)
Group of research
ARCO - Microarchitecture and Compilers
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants