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FEM: a step towards a common memory layout for FPGA based accelerators

Author
Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
Type of activity
Presentation of work at congresses
Name of edition
20th International Conference on Field Programmable Logic and Applications
Date of publication
2010
Presentation's date
2010-08
Book of congress proceedings
2010 International Conference on Field Programmable Logic and Applications: FPL 2010: 31 August-2 September 2010, Milano, Italy: proceedings
First page
568
Last page
573
DOI
https://doi.org/10.1109/FPL.2010.111 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5694312&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F5690273%2F5694025%2F05694312.pdf%3Farnumber%3D5694312 Open in new window
Abstract
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FPGA memory organizations to efficiently use the data fetched into the FPGA. This work presents a Front End Memory (FEM) layout based on BRAMs and Distributed RAM for FPGA-based accelerators. The presented memory layout serves as a template for various data organizations which is in fact a step towards the standardizatio...
Keywords
Field programmable gate arrays, Integrated circuit layout, Storage management
Group of research
CAP - High Performace Computing Group

Participants

  • Shafiq, Muhammad  (author and speaker )
  • Pericas Gleim, Miquel  (author and speaker )
  • Navarro, Nacho  (author and speaker )
  • Ayguade Parra, Eduard  (author and speaker )