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Mapping sparse matrix-vector multiplication (SMVM) on FPGA - reconfigurable supercomputing

Dickov, B.; Pericas, M.; Ayguade, E.; Navarro, Nacho
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
Fifth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
Any de l'edició
Data de presentació
Llibre d'actes
ACACES 2009: Advanced Computer Architecture and Compilation for Embedded Systems: poster abstracts: July 15, 2009: Terrassa, Spain
In many iterative solvers for systems of sparse linear equations Sparse Matrix­ Vector Multiplication (SMVM) is a critical computational kernel. In this work we use FPGA as a accelerator attached to a host processor (ALTIX supercomputer) to accelerate SMVM. However, due to the large data requirements performance heavily depends on by memory bandwidth which is very limited on the ALTIX platform. Input data are streamed through FIFO buffers, which simplifies portability to another platforms with...
Paraules clau
Compressed row storage, FPGA, Floating–point, Sparse matrix
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions


  • Dickov, Branimir  (autor ponent)
  • Pericas Gleim, Miquel  (autor ponent)
  • Ayguade Parra, Eduard  (autor ponent)
  • Navarro, Nacho  (autor ponent)