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Microarchitecture and Compilers for Future Processors III

Total activity: 7
Type of activity
Competitive project
Funding entity
Funding entity code
333.283,61 €
Start date
End date
clientes, clients, cloud computing, computación en la nube, consumo de energía, energy consumption, graphic processors, microarchitecture, microarquitectura, mobile processors, mobile systems, networks, performance, procesadores gráficos, procesadores móviles, redes, rendimiento, servers, servidores, sistemas móviles
The main objective of this project as for the researchers of the ARCO group is the research in the design of future microprocessors, taking into account
the determining factors of future technology, both for high performance processors and for commodity electronics.
This project is a continuation of that about to end, TIN2010-18368, from which it takes the name "Microarchitecture and Compilers for Future Processors"
and had as Main Investigator Prof. Antonio González Colas, who remains in the research group.
Fundamentally, two factors have determined the increased performance in processors: on one hand the technological advances in microprocessor
manufacturing and, on the other hand, the use of new and more efficient microarchitectural and compiler techniques. All these improvements bring a
number of challenges that are now considered as key in designing the processors for this upcoming decade: the limited instruction-level parallelism, the
interconnection network delays, high power consumption, heat dissipation, system relibility and security.
In this project we are going to address the influence of these issues in the research of future processors. Specifically, we will address six areas that we
consider fundamental: (1) the efficient design of circuits in the presence of unexpected changes in its operating parameters, (2) the efficient design of
graphic processors oriented to mobile devices, (3) the efficient implementation of virtual machines with low complexity but high computing power, (4) the
characterization and acceleration of emerging applications, (5) the design of new heterogeneous multiprocessor architectures that optimize the use of
the different processors depending on the types of application being executed, and (6) the study of new techniques in the design of the memory
hierarchy and interconnection networks to tolerate the increasing gap between the speeds of the various components of the computer.
We believe that the project fits perfectly within the Call for Projects I+D+i "Retos Investigación" in the "Programa Estatal de I+D+i orientada a los Retos
de la Sociedad". The challenge to which this project addresses is "Economía y Sociedad Digital" This project is framed within the improvement of ICT
and makes explicit reference to some of the priorities of the State Plan for Scientific Research, Technology and Innovation for the period 2013/2016,
such as Cloud Computing, and Network and Mobile Systems. The design of efficient architectures at both performance and energy consumption focused
to these environments will be the result from this research project.
Adm. Estat
Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016
Call year
Funcding program
Programa Estatal de I+D+i Orientada a los Retos de la Sociedad
Funding call
Retos de Investigación: Proyectos de I+D+i
Grant institution
Gobierno De España. Ministerio De Economía Y Competitividad, Mineco


Scientific and technological production

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