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EazyHTM: EAger-LaZY hardware transactional memory

Author
Tomic, S.; Perfumo, C.; Kulkami, C.; Armejach, A.; Cristal, A.; Unsal, O.; Harris, T.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
42nd Annual IEEE/ACM International Symposium on Microarchitecture
Date of publication
2009
Presentation's date
2009-12
Book of congress proceedings
MICRO-50: the 50th Annual IEEE/ACM International Symposium on Microarchitecture: proceedings: October 14-18, 2017, Cambridge, MA
First page
145
Last page
155
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5375348 Open in new window
Abstract
Transactional memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overheads than implementations in software, and refinements in conflict management strategies for HTM allow for even larger improvements. In particular, lazy conflict management has been shown to deliver better performance, but it has hitherto required complex protocols and implementations. In this paper we show a new scalable H...
Keywords
EazyHTM, Transactional memory
Group of research
CAP - High Performace Computing Group

Participants

  • Tomic, Saša  (author and speaker )
  • Perfumo, Cristian  (author and speaker )
  • Kulkarni, Chinmay  (author and speaker )
  • Armejach Sanosa, Adria  (author and speaker )
  • Cristal Kestelman, Adrian  (author and speaker )
  • Unsal, Osman Sabri  (author and speaker )
  • Harris, Tim  (author and speaker )
  • Valero Cortes, Mateo  (author and speaker )