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J-DSE: Joint software and hardware design space exploration for application specific processors

Paolieri, M.; Bonesana, I.; Gioiosa, R.; Valero, M.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
The 3rd Workshop on Programmability Issues for Multi-Core Computers
Any de l'edició
Data de presentació
Llibre d'actes
Third Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG-3): January 24, 2010, Pisa, Italy
Modern embedded systems’ applications are characterized by a high demand of computing power but classical embedded systems’ constraints (power, area, etc.) still hold. The solution to this new challenge comes from the use of Multi-Core in embedded systems. However, providing high performance with a limited power consumption is still an open problem especially considering the rapid increase of design complexity and manufacturing cost. The use of customizable cores (like FPGAs and ASIPs) that ...
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions


  • Paolieri, Marco  (autor ponent)
  • Bonesana, I.  (autor ponent)
  • Gioiosa, Roberto  (autor ponent)
  • Valero Cortes, Mateo  (autor ponent)