Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Architectural support for fair reader-writer locking

Autor
Vallejo, E.; Beivide, R.; Cristal, A.; Harris, T.; Vallejo, F.; Unsal, O.; Valero, M.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
43rd Annual IEEE/ACM International Symposium on Microarchitecture
Any de l'edició
2010
Data de presentació
2010-12
Llibre d'actes
The 43rd Annual IEEE/ACM International Symposium on Microarchitecture: Atlanta, Georgia, 4-8 December 2010: proceedings
Pàgina inicial
275
Pàgina final
286
DOI
https://doi.org/10.1109/MICRO.2010.12 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5695543 Obrir en finestra nova
Resum
Many shared-memory parallel systems use lock-based synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are inefficient either in memory usage, lock transfer time, or both. Proposed hardware locking mechanisms are either too specific (for example, requiring static assignment of threads to cores and vice-versa), support a limited number of concurrent locks, require tag values to be associated with every memory location, rely on the low...
Paraules clau
Fairness, Lock control unit, Reader-writer locks
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Vallejo, Enrique  (autor ponent)
  • Beivide Palacio, Ramon  (autor ponent)
  • Cristal Kestelman, Adrian  (autor ponent)
  • Harris, Tim  (autor ponent)
  • Vallejo, Fernando  (autor ponent)
  • Unsal, Osman Sabri  (autor ponent)
  • Valero Cortes, Mateo  (autor ponent)