Loading...
Loading...

Go to the content (press return)

A flexible hybrid transactional memory multicore on FPGA

Author
Arcas, O.; Sonmez, N.; Unsal, O.; Cristal, A.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
XXII Jornadas de Paralelismo
Date of publication
2011
Presentation's date
2012-09
Book of congress proceedings
XXII Jornadas de Paralelismo: La Laguna, 7-9 septiembre 2011: actas
First page
283
Last page
289
URL
http://jp2011.pcg.ull.es/actas Open in new window
Abstract
In this paper we present the design and implementation of an MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our exible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we acc...
Group of research
CAP - High Performace Computing Group

Participants