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Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

Autor
Upasani, G.; Vera, F.J.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
41st International Symposium on Computer Architecture
Any de l'edició
2014
Data de presentació
2014-06-14
Llibre d'actes
ISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA
Pàgina inicial
37
Pàgina final
48
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ISCA.2014.6853200 Obrir en finestra nova
Projecte finançador
MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
Microarquitectura i compiladors (ARCO)
TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS
Repositori
http://hdl.handle.net/2117/24576 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853200 Obrir en finestra nova
Resum
The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling soft errors in the logic and memories that allow meeting the desired failures-in-time (FIT) target are key to keep harnessing the benefits of Moore's law. The failure to scale the soft error rate caused by particle strikes, may soon limit the total number of cores that one may ha...
Citació
Upasani, G.; Vera, X.; González, A. Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. A: International Symposium on Computer Architecture. "ISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA". Minneapolis: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 37-48.
Paraules clau
Acoustic waves, Acoustics, Cache hierarchies, Computer architecture, Detected unrecoverable errors, Detection latency, Error correction, Microprocessor chips, Operating voltage, Radiation hardening, Reliability techniques, Scalable architectures, Silent data corruptions, Soft error rate, Voltage scaling
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants

Arxius