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Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

Author
Upasani, G.; Vera, F.J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
41st International Symposium on Computer Architecture
Date of publication
2014
Presentation's date
2014-06-14
Book of congress proceedings
ISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA
First page
37
Last page
48
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ISCA.2014.6853200 Open in new window
Project funding
MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
Microarquitectura i compiladors (ARCO)
TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS
Repository
http://hdl.handle.net/2117/24576 Open in new window
URL
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853200 Open in new window
Abstract
The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling soft errors in the logic and memories that allow meeting the desired failures-in-time (FIT) target are key to keep harnessing the benefits of Moore's law. The failure to scale the soft error rate caused by particle strikes, may soon limit the total number of cores that one may ha...
Citation
Upasani, G.; Vera, X.; González, A. Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. A: International Symposium on Computer Architecture. "ISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA". Minneapolis: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 37-48.
Keywords
Acoustic waves, Acoustics, Cache hierarchies, Computer architecture, Detected unrecoverable errors, Detection latency, Error correction, Microprocessor chips, Operating voltage, Radiation hardening, Reliability techniques, Scalable architectures, Silent data corruptions, Soft error rate, Voltage scaling
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Upasani, Gaurang  (author and speaker )
  • Vera Rivera, Francisco Javier  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )

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