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Efficient power gating of SIMD accelerators through dynamic selective devectorization in an HW/SW codesigned environment

Author
Kumar, R.; Martinez, A.; Gonzalez, A.
Type of activity
Journal article
Journal
ACM transactions on architecture and code optimization
Date of publication
2014-10-01
Volume
11
Number
3
First page
25:1
Last page
25:23
DOI
https://doi.org/10.1145/2629681 Open in new window
Abstract
Leakage energy is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this energy Therefore, reducing functional unit leakage has received much attention in recent years. Power gating is one of the most widely used techniques to minimize leakage energy. Power gating turns off the functional units during the idle periods to reduce the leakage. Therefore, the amount of leakage energy savings is directly proportional t...
Keywords
Algorithms, Devectorization, Experimentation, Hardware/software codesigned processors, Leakage, Performance, Power gating
Group of research
ARCO - Microarchitecture and Compilers

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