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VSR sort: a novel vectorised sorting algorithm and architecture extensions for future microprocessors

Author
Hayes, T.; Palomar, O.; Unsal, O.; Cristal, A.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
21st IEEE International Symposium on High Performance Computer Architecture
Date of publication
2015
Presentation's date
2015-02
Book of congress proceedings
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA 2015): Burlingame, California, USA: 7-11 February 2015
First page
26
Last page
38
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/HPCA.2015.7056019 Open in new window
Repository
http://hdl.handle.net/2117/77204 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7056019 Open in new window
Abstract
Sorting is a widely studied problem in computer science and an elementary building block in many of its subfields. There are several known techniques to vectorise and accelerate a handful of sorting algorithms by using single instruction-multiple data (SIMD) instructions. It is expected that the widths and capabilities of SIMD support will improve dramatically in future microprocessor generations and it is not yet clear whether or not these sorting algorithms will be suitable or optimal when exe...
Citation
Hayes, T., Palomar, O., Unsal, O., Cristal, A., Valero, M. VSR sort: a novel vectorised sorting algorithm and architecture extensions for future microprocessors. A: International Symposium on High-Performance Computer Architecture. "2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA 2015): Burlingame, California, USA: 7-11 February 2015". San Francisco Bay Area, California: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 26-38.
Keywords
Digital arithmetic, Microprocessor chips, Parallel architectures, Sorting
Group of research
CAP - High Performace Computing Group

Participants