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Feasibility of Embedded DRAM Cells on FinFET Technology

Author
Amat, Esteve; Calomarde, A.; Moll, F.; Canal, R.; Rubio, A.
Type of activity
Journal article
Journal
IEEE transactions on computers
Date of publication
2016-04-01
Volume
65
Number
4
First page
1068
Last page
1074
DOI
https://doi.org/10.1109/TC.2014.2375204 Open in new window
Project funding
Multilevel approach to the reliability-aware design of analog and digital integrated circuits
Terascale Reliable Adaptive Memory System
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977916 Open in new window
Abstract
In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/p FinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the...
Keywords
CMOS, DEVICES, FinFET, LOGIC, SRAM, eDRAM and temperature
Group of research
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants