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iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches

Author
Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
Type of activity
Presentation of work at congresses
Name of edition
32nd IEEE International Conference on Computer Design
Date of publication
2014
Presentation's date
2014
Book of congress proceedings
2014 32nd IEEE International Conference on Computer Design (ICCD): October 19 - 22, 2014 Seoul, Korea
First page
68
Last page
74
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ICCD.2014.6974664 Open in new window
Project funding
Design And Test Principles For Terascale Integrated Systems
MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
Repository
http://hdl.handle.net/2117/26673 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6974664 Open in new window
Abstract
Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical variations of process parameters, it can potentially render systems dysfunctional in certain scenarios. Data caches suffer the most from such phenomenon because of the unbalanced duty cycle ratio of SRAM cells and maximum intrinsic susceptibility to process variations. In...
Citation
Ganapathy, S. [et al.]. iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches. A: IEEE International Conference on Computer Design. "2014 32nd IEEE International Conference on Computer Design (ICCD): October 19 - 22, 2014 Seoul, Korea". Seoul: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 68-74.
Keywords
Cache storage, Elemental semiconductors, Integrated circuit design, Integrated circuit reliability, Logic design, SRAM chips, Silicon
Group of research
ARCO - Microarchitecture and Compilers
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

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